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73M1903C Modem Analog Front End
DATA SHEET
JANUARY 2008
DESCRIPTION
The TERIDIAN 73M1903C Analog Front End (AFE) IC includes fully differential hybrid driver outputs, which connect to the telephone line interface through a transformer-based DAA. The receive pins are also fully differential for maximum flexibility and performance. This arrangement allows for the design of a high performance hybrid circuit to improve signal to noise performance under low receive level conditions, and compatibility with any standard transformer intended for PSTN communications applications. The device incorporates a programmable sample rate circuit to support soft modem and DSP based implementations of all speeds up to V.92 (56kbps). The sampling rates supported are from 7.2kHz to 16.0kHz by programming the prescaler NCO and the PLL NCO. The TERIDIAN 73M1903C device incorporates a digital host interface that is compatible with the serial ports found on most commercially available DSPs and processors and exchanges both payload and control information with the host. This interface can be configured as a single master/slave mode or as a daisy chain mode that allows the user to connect up to eight 73M1903C devices to a single host for multi Analog Front End applications, such as, central server modems. Costs saving features of the device include an input reference frequency circuit, which accepts a range of crystals from 4.9-27MHz. It also accepts external reference clock values between 1MHz40MHz generated by the host processor. In most applications, this eliminates the need for a dedicated crystal oscillator and reduces the bill of materials (BOM). The 73M1903C also supports two analog loop back and one digital loop back test modes.
Features
* * * * * * * * * * * * Two pairs of software selectable transmit differential outputs for worldwide impedance driver implementations. Up to 56kbps (V.92) performance Programmable sample rates (7.2-16.0kHz) Reference clock range of 1-40MHz Crystal frequency range of 4.9-27MHz Master or slave mode operation and daisy chain configurable synchronous serial Host interface Low power modes Fully differential receiver and transmitter Drivers for transformer interface 3.0V - 3.6V operation 5V tolerant I/O Industrial temperature range (-40 to +85C) JATE compliant transmit spectrum Package options: 32 pin QFN
*
Applications
* * * * * * * * * * * * Central site server modems Set Top Boxes Personal Video Recorders (PVR) Multifunction Peripherals (MFP) Fax Machines Internet Appliances Game Consoles Point of Sale Terminals Automatic Teller Machines Speaker Phones Digital Answering Machines RF Modems
VBG (HYBRID) TXAP1 TXAN1 TXAP2 TXAN2 RXAP RXAN Transmit Drivers/ Filters Receiver MUX/ Filters Analog Sigma Delta Ref. SCLK Control Registers SDIN Serial Port SDOUT FS Control Logic FSD
DAC
GPIO HOOK
DAA controls
Clock
Crystal
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
Table of Contents
DESCRIPTION.............................................................................................................................................. 1 Features ........................................................................................................................................................ 1 Applications................................................................................................................................................... 1 SIGNAL DESCRIPTION ............................................................................................................................... 4 SERIAL INTERFACE .................................................................................................................................... 5 CONTROL REGISTER MAP ...................................................................................................................... 11 SYSTEM CONTROL REGISTERS............................................................................................................. 12 GPIO REGISTERS ..................................................................................................................................... 13 PLL CONFIGURATION REGISTERS......................................................................................................... 14 CLOCK GENERATION ............................................................................................................................... 17 ANALOG I/O ............................................................................................................................................... 20 MODEM TRANSMITTER............................................................................................................................ 21 MODEM RECEIVER ................................................................................................................................... 24 TEST MODES............................................................................................................................................. 28 POWER SAVING MODES.......................................................................................................................... 28 ELECTRICAL SPECIFICATIONS............................................................................................................... 29 ABSOLUTE MAXIMUM RATINGS.......................................................................................................... 29 RECOMMENDED OPERATING CONDITIONS...................................................................................... 29 DIGITAL SPECIFICATIONS ....................................................................................................................... 30 DC CHARACTERISTICS ........................................................................................................................ 30 AC TIMING .............................................................................................................................................. 31 ANALOG SPECIFICATIONS ...................................................................................................................... 32 DC SPECIFICATIONS ............................................................................................................................ 32 AC SPECIFICATIONS............................................................................................................................. 32 PERFORMANCE..................................................................................................................................... 33 PACKAGE OPTIONS.................................................................................................................................. 35 MECHANICAL DRAWINGS........................................................................................................................ 36 73M1903C DAA Resistor Calculation Guide........................................................................................... 37 APPENDIX B............................................................................................................................................... 40 Crystal Oscillator ..................................................................................................................................... 40 PLL .......................................................................................................................................................... 41 Examples of NCO settings ...................................................................................................................... 42 ORDERING INFORMATION....................................................................................................................... 46
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
List of Figures
Figure 1: SCLK and FS with SckMode=0.................................................................................................. 7 Figure 2: Control frame position vs. SPOS .............................................................................................. 7 Figure 3: Serial Port Timing Diagrams...................................................................................................... 8 Figure 4: 73M1903C Host connection in master and slave mode ................................................................ 9 Figure 5: 73M1903C Daisy chaining for master/slave mode and slave modes .................................... 9 Figure 6: Clock Generation ......................................................................................................................... 17 Figure 7: Analog block diagram .................................................................................................................. 20 Figure 8: Overall TX path frequency response at 8kHz sample rate.......................................................... 21 Figure 9: Frequency response of TX path for DC to 4kHz in band signal at 8kHz sample rate........ 22 Figure 10: Overall receiver frequency response at 8kHz sample rate................................................. 25 Figure 11: Rx passband response at 8kHz sample rate........................................................................ 26 Figure 12: RXD Spectrum of 1kHz tone .................................................................................................. 27 Figure 13: RXD Spectrum of 0.5kHz, 1kHz, 2kHz, 3kHz and 3.5kHz tones of Equal Amplitudes...... 27 Figure 14: Serial Port Data Timing .......................................................................................................... 31 Figure 15: Typical DAA block diagram........................................................................................................ 37 Figure 16: Single transmitter arrangement ................................................................................................. 38 Figure 17: Dual transmitter arrangement .................................................................................................... 39 Figure 18: NCO block diagram ................................................................................................................... 40 Figure 19: PLL Block Diagram .................................................................................................................... 41
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
PIN DESCRIPTION
The TERIDIAN 73M1903C modem Analog Front End (AFE) IC is available in a 32 pin QFN package. The following table describes the function of each pin. There are three pairs of power supply pins, VPA (analog), VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source in order to isolate digital noise from the analog circuits internal to the chip. VPPLL can be directly connected to VPD. Failure to adequately isolate and decouple these supplies will compromise device performance.
PIN NAME VND VNA VPD VPA VPPLL VNPLL TYPE GND GND PWR PWR PWR PWR PIN # 1, 22 16 2, 25 9 20 17 DESCRIPTION Negative Digital Ground Negative Analog Ground Positive Digital Supply Positive Analog Supply Positive PLL Supply, shared with VPD Negative PLL Ground Master reset. When this pin is a logic 0 all registers are reset to their default states; Weak-pulled high-default. A low pulse longer than 100ns is needed to reset the device. The device will be ready within 100us after this pin goes to logic 1 state. Crystal oscillator input. When providing an external clock source, drive OSCIN. Crystal oscillator circuit output pin. Software definable digital input/output pins. Receive analog negative input. Receive analog positive input. Transmit analog negative output 1 Transmit analog negative output 2 Transmit analog positive output 1 Transmit analog positive output 2 Serial interface clock. With master mode and SCLK continuous selected, Freq = 256*Fs ( =2.4576MHz for Fs=9.6kHz). For slave mode, this pin must be pulled down by a resistor (<4.7k). Serial data output (or input to the host). Serial data input (or output from the host) Frame synchronization. (Active Low) Type of frame sync. 0 = late (mode0); 1 = early (mode1). Weak-pulled high - default Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK Continuous; tied low = 32 clocks per R/W cycle. Delayed frame sync to support daisy chain mode with additional 73M1903C devices
RST
I
26
OSCIN OSCOUT GPIO(0-7) RXAN RXAP TXAN1 TXAN2 TXAP1 TXAP2 SCLK SDOUT SDIN FS TYPE SckMode FSD
I O I/O I I O O O O I/O O I O I I O
19 18 3, 4, 5, 6, 23 24, 30, 31 14 15 10 11 12 13 8 32 29 7 27 28 21
Table 1: 32 QFN Pin Description
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
MODEM ANALOG FRONT END (MAFE) SERIAL INTERFACE The MAFE (Modem Analog Front End) serial data port is a bi-directional port that can be supported by most DSPs. The typical I2S (Inter-IC Sound, NXP semiconductor) bus can be easily converted into MAFE compatible interface. The 73M1903C can be configured either as a master or a slave of the serial interface. When the 73M1903C is configured as a master device, it generates a serial bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that can be programmed by the user. In master mode, the serial bit clock is always derived by dividing the system clock by 18. The Sclk rate, Fsclk, is related to the frame synchronization rate (sample rate), Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which both transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions. They are: 1. Fxtal1 = 27MHz, Fs1 = 7.2kHz 2. Fxtal2 = 18.432MHz, Fs2 = 8kHz. 3. Fxtal3 = 24.576MHz, Fs3 = 9.6kHz Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18. Examples: 1. If Fxtal1 = 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz. 2. If Fxtal2 = 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz. 3. If Fxtal3 = 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz. When 73M1903C is programmed through the serial port to a desired Fs and the PLL has settled out, the system clock will transition to the PLL-based clock in a glitch-less manner. Examples: 1. If Fs1 = 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz. 2. If Fs2 = 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz. 3. If Fs3 = 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz. This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front end, the chip will automatically run off the crystal until the host forces the transition by setting Frcvco bit (Bit 7 in Register0E). The transition should be forced on or after the second frame synch period following the write to a designated PLL programming registers (Register08 to Register0D). When reprogramming the PLL the host should first transition the system clock to the crystal before reprogramming the PLL so that any transients associated with it will not adversely impact the serial port communication. Power saving is accomplished by disabling the analog front end by clearing ENFE bit (bit 7 Register00). During the normal operation, a data frame sync signal (FS) is generated by the 73M1903C at the rate of Fs. For every data FS there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin programmable for type. FS can either be early or late determined by the state of the TYPE input pin. When Type pin is left open, an early FS is generated in the bit clock prior to the first data bit transmitted or received. When held low, a late FS operates as a chip select; the FS signal is active for all bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines the frame synchronization mode used.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
SERIAL DATA AND CONTROL
The bits transmitted on the SDOUT pin are defined as follows: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 If the HC bit (Bit 0 of Register01) is set to zero, the 16 bits that are received on the SDIN are defined as follows: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 In this case LSB(TX0) in a transmit bit stream is forced to 0 automatically. bit3 TX3 bit2 TX2 bit1 TX1 bit0 CTL
If the Hardware Control bit (Bit 0 of Register 01) is set to one, the 16 bits that are received on the SDIN input are defined as follows: bit15 bit14 bit13 bit12 bit11 bit10 bit9 TX15 TX14 TX13 TX12 TX11 TX10 TX9 bit8 TX8 bit7 TX7 bit6 TX6 bit5 TX5 bit4 TX4 bit3 TX3 bit2 TX2 bit1 TX1 bit0 TX0
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data frames. If the hardware control bit is set to zero, CTL is used by software to request a control frame. If CTL is high, a control frame will be initiated before the next data frame. A control frame allows the controller to read or write status and control to the 73M1903C. The control word received on the SDIN pin is defined as follows: bit15 bit14 bit13 bit12 bit11 bit10 R/W A6 A5 A4 A3 A2 bit9 A1 bit8 A0 bit7 D7 bit6 D6 bit5 D5 bit4 D4 bit3 D3 bit2 D2 bit1 D1 bit0 D0
The control word transmitted on the SDOUT pin is defined as follows: bit15 bit14 bit13 bit12 bit11 bit10 0 0 0 0 0 0 bit9 0 bit8 0 bit7 D7 bit6 D6 bit5 D5 bit4 D4 bit3 D3 bit2 D2 bit1 D1 bit0 D0
If the R/W bit (Bit15 of control word) is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data contained in the register pointed to by address bits A6-A0. Only one control frame can occur between any two data frames. Writes to unimplemented registers are ignored. Reading an unimplemented register returns an unknown value. The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is set to a 0 the control frames occur mid way between data frames, i.e., the time between data frames is equal. If SPOS is set to a 1, the control frame is 1/4 of the way between consecutive data frames, i.e., the control frame is closer to the first data frame. This is illustrated in Figure 2. The TERIDIAN 73M1903C modem AFE IC includes a feature that shuts off the serial clock (SCLK) after 32 cycles of SCLK following the frame synch (figure 1). The SckMode pin controls this mode. If this pin is left open the clock will run continuously. If SckMode is set low, the clock will be gated on for 32 clocks
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
for each FS. The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN pin is sampled on the falling edge of SCLK. Figure 3 shows the timing diagrams for the serial port.
32 Cycles of SCLK
SCLK
FS ( early mode)
SCLK Relative to early FS
32 Cycles of SCLK
SCLK
FS ( late mode)
SCLK Relative to late FS
Figure 1: SCLK and FS with SckMode=0
DATA FRAMES SPOS = 0
SPOS = 1
CONTROL FRAMES
Figure 2: Control frame position vs. SPOS
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
SCLK FS SDIN SDOUT
TX15
RX15
TX14 RX14
TX13 RX13
TX12 RX12
TX11 RX11
TX10 RX10
TX9 RX9
TX8 RX8
TX7 RX7
TX6 RX6
TX5 RX5
TX4 RX4
TX3 RX3
TX2 RX2
TX1 RX1
CTL RX0
Data Frame with earlyl Frame Sync
SCLK FS SDIN SDOUT
TX15
RX15
TX14 RX14
TX13 RX13
TX12 RX12
TX11 RX11
TX10 RX10
TX9 RX9
TX8 RX8
TX7 RX7
TX6 RX6
TX5 RX5
TX4 RX4
TX3 RX3
TX2 RX2
TX1 RX1
CTL RX0
Data Frame with late Frame Sync
SCLK FS SDIN SDOUT
R/W zero A6 zero A5 zero A4 zero A3 zero A2 zero A1 zero A0 zero DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 DI3 DO3 DI2 DO2 DI1 DO1 DI0 DO0
Control Frame with early Frame Sync
SCLK FS SDIN SDOUT
R/W zero A6 zero A5 zero A4 zero A3 zero A2 zero A1 zero A0 zero DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 DI3 DO3 DI2 DO2 DI1 DO1 DI0 DO0
Control Frame with late Frame Sync
Sample Rate SCLK FS SDIN SDOUT
1
TX RX TX RX TX RX TX RX TX RX
16
1 RX
128
R 0 A 0 A 0 DI DO DI DO
144
A 0 DI DO
256
1
TX RX TX RX TX RX TX RX TX RX 0 RX
Data Frame
Control Frame
Data Frame
Relation Between the Data and Control Frames (Master Mode, continuous clock, default SPOS)
Figure 3: Serial Port Timing Diagrams
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
SLAVE MODE AND DAISY CHAIN
If the SCLK pin is externally pulled down to ground by a <4.7K resistor, the 79M1903C device is in the slave mode, after reset. In this mode of operation the serial clock (SCLK) and FS are inputs to 79M1903C provided by the Master device. The serial clock input must be connected to OSCIN pin while SCLK pin of 73M1903C is unconnected, except for the resistor connected to ground (see Figures 4 and 5). The 73M1903C PLL must be programmed to multiply the serial clock frequency by an appropriate factor in order to obtain Fsys. Therefore the serial clock has to be continuous and without low frequency jitter (the high frequency jitter is rejected by the 79M1903C PLL). The SckMode pin is not used since the Master device provides FS and serial clock.
MCLK SDOUT
73M1903C
OSCIN SDIN SDOUT FS SCLK SckMode TYPE "1/0" "1/0" (Master) SCLK SDOUT
73M1903C
OSCIN SDIN SDOUT FS SCLK SckMode TYPE "x" "x" (Slave)
HOST
(Slave)
SDIN FS SCLK
HOST
(Master)
SDIN FS
"x" : don't care
73M1903C Master Mode
73M1903C Slave Mode
Figure 4: 73M1903C Host connection in master and slave mode
MCLK SDOUT
73M 1903C
OSCIN (Master) SDIN SDOUT FS SCLK FSBD SckMode TYPE "1/0" "1/0"
SCLK SDOUT
73M 1903C
OSCIN (Slave) SDIN SDOUT FS SCLK FSBD SckMode TYPE "x" "x"
HOST
(Slave)
SDIN FS SCLK
HOST
(Master)
SDIN FS
OSCIN SDIN
73M 1903C
(Slave) "x" : don't care SDOUT FS SCLK SckMode TYPE "x" "x"
OSCIN SDIN
73M 1903C
(Slave)
SDOUT FS SCLK SckMode TYPE "x" "x"
Daisy chain for M aster/Slave mode
Daisy chain for Slave mode
Figure 5: 73M1903C Daisy chaining for master/slave mode and slave modes In order to daisy chain two or more 73M1903C devices, the master must be programmed into hardware controlled control frame mode by setting the HC bit (bit 0 in Register01) to "1", then set FSDEn (bit 3 in Register06), and then set CkoutEn bit (bit 3 in Register01) to allow the FSD to come through. The first
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
frame after enabling FSD must be Data. For the two daisy chained devices, the data/control frames are 32 bits. The first 16 bits go to the first device; the next 16 bits go to the second device in the chain, as timed by FSD of the first device. For four daisy-chained devices, the data/control frames are 64 bits. The first 16 bits go to the first device in the chain; the next 16 bits go to the second device in the chain as started by FSD of the first device, etc. FSD is always "Late Type" frame sync. Up to eight 73M1903C devices may be daisy-chained if the control frame sync is placed at the middle of the data frame sync interval. Four devices may be daisy-chained if the control frame sync is placed at the 1/4 of the data frame sync interval. In all cases involving slave and daisy chain operation, only hardware controlled Control Frames can be supported. Software requested control frames are not allowed. In slave mode the relationship of Fs and Fsclk is Fsclk/Fs, with a range of from 96 to 256 SCLKs per Fs. Again, the host controls the relationship of FS to SCLK, with the condition that Fsclk>750kHz and Fsys=4608*Fs. The 79M1903C PLL must be programmed to generate Fsys with those conditions. To program the 73M1903C NCOs, OSCIN (Fsclk)=SCLK=Fref when Pdvsr=1 and Prst=0 in the calculations. Fsys in the previous discussion is Fvco in the calculations which is equal to 4608*Fs. For example, two typical cases are Fsclk=256*Fs and Fsclk=144*Fs. For the case when Fsclk=256*Fs and Fs=8kHz, the 79M1903C PLL has to be set to Fsys=4608*Fs=36.864MHz, and Sclk=256*8kHz=2.048MHz. Therefore Ndvsr=36.864/2.048=18 (12h) and Nrst=0 For the case when Fsclk=144*Fs and d Fs=8kHz, the 79M1903C PLL has to be set to Fsys=4608*Fs=36.864MHz and Sclk=144*8kHZ=1.152MHz. Therefore Ndvsr=36.864/1.152=32 (20h) and Nrst=0
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
CONTROL REGISTER MAP
The following Table 2 shows the map of addressable registers in the 73M1903C. Each register and its bits are described in detail in the following sections.
Register Name CTRL TEST DATA DIR Register04 Register05 REV Register07 PLL_PSEQ PLL_RST PLL_KVCO PLL_DIV PLL_SEQ XTAL_BIAS
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh
Default 08h 00h FFh FFh 00h 00h 60h 00h 00h 0Ah 22h 12h 00h C0h
BIT 7 ENFE TMEN GPIO7 DIR7
BIT 6 SELTX2 DIGLB GPIO 6 DIR6
BIT 5
BIT 4
BIT 3 TXDIS CkoutEn GPIO 3 DIR3
BIT 2
BIT 1
BIT 0 RXGAIN HC GPIO 0 DIR0
TXBST(1:0) ANALB GPIO 5 DIR5 INTLB GPIO 4 DIR4
RXG(1:0) RXPULL GPIO 2 DIR2 SPOS GPIO 1 DIR1
Reserved Reserved Rev(3:0) FSDEn Reserved Pseq(7:0) Prst(2:0) Ichp(3:0) Xtal(1:0) Reserved Reserved Ndvsr(6:0) Nseq(7:0) Nrst(2:0) Pdvsr(4:0) Kvco(2:0) Reserved
PLL_LOCK 0Eh 00H Frcvco PwdnPll LockDet Note: Register or bit names in bold underline denotes the READ ONLY bits and registers. Register bits marked "-" are not used. Writing any value to these bits won't affect the operation. Reserved are bits reserved for factory test purpose only. Do not attempt to write these locations to values other than their default to prevent unexpected operation. Register Bit notations used in this document are as follows. - Registerxx: Register05 represents the register with Address 0x05 - BIT(s)NAME(MSB:LSB) ; Rev(3:0) represents 4 bits of Rev3, Rev2, Rev1 and Rev0. -(RegisterAddress[BIT(s)]) ; (0X00[7]) represents Bit 7 of Register address 0x00, ENFE bit (0X06[7:4]) represents Bit 7, Bit 6, Bit 5 and Bit4 of Register address 06, Rev(3:0).
Table 2: Register Map
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
SYSTEM CONTROL REGISTERS Register00 (CTRL): Address 00h
Reset State 08h BIT 7 BIT 6 ENFE SelTX2 ENFE BIT 5 TXBST BIT 4 TXBST0 BIT 3 TXDIS BIT 2 RXG1 BIT 1 RXG0 BIT 0 RXGAIN
SelTX2 TXBST1
TXBST0 TXDIS RXG(1:0)
RXGAIN
(0X00[7]) Enable Front End. 1 = Enable the digital filters and analog front end. 0 = Disable the analog blocks shut off the clocks to the digital and analog receive/transmit circuits. (0X00[6]) Select Tx driver 2 1 = Selects Secondary transmitter (TXAP2 and TXAN2) if TXDIS=0 0 = Selects Primary transmitter (TXAP1 andTXAN1) if TXDIS=0 (0X00[5]) 1 = Add a gain of 1.335dB (16.6%) to the transmitter; also the common mode voltage of the transmit path is increased to 1.586V. This is intended for enhancing DTMF transmit power only and should not be used in data mode. 0 = No gain is added (0X00[4]) 1 = A gain of 1.65dB(21%) is added to the transmitter 0 = The gain of the transmitter is nominal (0X00[3]) 1 = Tri-state the TXAP1,2 and TXAN1,2 pins, provides a bias of VBG into 80 k for each output pin (0X00[2:1]) Rx Gain Selection 00 = 6 dB Receive Gain 01 = 9 dB 10 = 12 dB 11 = 0 dB (0X00[0]) 20 dB RxGain Enable. This gain selection can be used for line snoop or Caller ID detection. 1 = Increase the gain of the receiver by 20 dB. 0 = Normal operation
Register01 (TEST): Address 01h
Reset State 00h BIT 7 BIT 6 TMEN DIGLB TMEN DIGLB BIT 5 ANALB BIT 4 INTLB BIT 3 CkoutEn BIT 2 RXPULL BIT 1 SPOS BIT 0 HC
ANALB
(0X01[7]) Test Mode Enable. 0 = Normal operation 1 = Enable test modes. (0X01[6]) Digital Loop back Enable 0 = Normal operation 1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter input. (0X01[5]) Analog Loop back Enable 0 = Normal operation 1 = Tie the analog output of the transmitter to the analog input of the receiver.
(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73M1903C Modem Analog Front End
DATA SHEET
INTLB (0X01[4]) Internal Loop back Enable. (Remote Analog Loop back) 0 = Normal operation 1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter input. (0X01[3]) Clock Output Enable 1= Enable the CLKOUT output; This bit must be set after the FSDEn bit is set to enable daisy chain mode. 0= CLKOUT tri-stated, for normal operation. (0X01[2]) 1= Pulls DC Bias to RXAP/RXAN pins, thru 100Kohm each, to VREF, to be used in testing Rx path. 0= No DC Bias to RXAP/RXAN pins (0X01[1]) 1= Control frames occur after one quarter of the time between data frames has elapsed. 0= Control frames occur half way between data frames. (0X01[0]) 1= Control frame generation is under hardware control, bit 0 of data frames on SDIN is bit 0 of the transmit word and control frames happen automatically after every data frame. 0= Control frame generation is under software control, bit 0 of data frames on SDIN is a control frame request bit and control frames happen only on request.
CkoutEn
RXPULL
SPOS HC
Register06 (REV): Address 06h
Reset State 60h BIT 7 BIT 6 BIT 5 Rev(3:0) Rev(3:0) FSDEn BIT 4 BIT 3 FSDEn BIT 2 BIT 1 Reserved BIT 0
(0X06[7:4]) Contain the revision ID of the TERIDIAN 73M1903C device. The rest of this register is for chip development purposes only and is not intended for customer use. Do not write to shaded locations. (0X06[3]) Delayed Frame Sync Enable. This bit shall be enabled if the daisy chain mode is used. 1 = Delayed frame sync for daisy chaining of additional 73M1903C devices. 0 = FSD tristated, for normal operation.
GPIO REGISTERS
The TERIDIAN 73M1903C modem AFE device provides 8 user definable I/O pins. Each pin is programmed separately as either an input or an output by a bit in a direction register. If the bit in the direction register is set high, the corresponding pin is an input whose value is read from the GPIO data register. If it is low, the pin will be treated as an output whose value is set by the GPIO data register. To avoid unwanted current contention and consumption in the system from the GPIO port before the GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins. The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
Register02 (DATA): Address 02h
Reset State FFh BIT 7 BIT 6 GPIO7 GPIO6 GPIO(7:0) BIT 5 GPIO5 BIT 4 GPIO4 BIT 3 GPIO3 BIT 2 GPIO2 BIT 1 GPIO1 BIT 0 GPIO0
(0X02[7:0]) Bits in this register will be asserted on the GPIO(7:0) pins if the corresponding direction register bit is a 0. Reading this address will return data reflecting the values of pins GPIO(7:0).
Register03 (DIR): Address 03h
Reset State FFh BIT 7 BIT 6 DIR7 DIR6 DIR(7:0) BIT 5 DIR5 BIT 4 DIR4 BIT 3 DIR3 BIT 2 DIR2 BIT 1 DIR1 BIT 0 DIR0
(0X03[7:0]) This register is used to designate the GPIO pins as either inputs or outputs. If the register bit is reset to `0', the corresponding GPIO pin is programmed as an output. If the register bit is set to a "1", the corresponding pin will be configured as an input.
PLL CONFIGURATION REGISTERS Register08 (PLL_PSEQ): Address 08h
Reset State 00h BIT 7 BIT 6 Pseq(7:0) BIT 5 BIT 4 BIT 3 Pseq(7:0) BIT 2 BIT 1 BIT 0
(0X08[7:0]) This corresponds to the sequence of divisor. If Prst(2:0) setting in Register09 is 00, this register is ignored.
Register09 (PLL_RST): Address 09h
Reset State 0Ah BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Prst(2:0) Pdvsr(4:0) Prst(2:0) represents the rate at which the sequence register is reset. Pdvsr(4:0) represents the divisor. BIT 1 BIT 0
Register0A (PLL_KVCO): Address 0Ah
Reset State 22h BIT 7 BIT 6 Ichp(3:0) BIT 5 BIT 4 BIT 3
Reserved
BIT 2
BIT 1
Kvco(2:0)
BIT 0
Ichp(3:0)
(0X0A[:47]) represents the size of the charge pump current in the PLL. This charge pump current can be calculated with Ichp = 2.0A* (2 + Ichp0 + Ichp1 * 21 + Ichp2 * 22+Ichp3 * 2^3 )* (T/To), where To=300 C and T=Temperature in K. Bit 3 is a reserved control bit. This bit shall remain "0" always. Kvco(2:0) (0X0A[2:0]) Represents the magnitude of Kvco associated with the VCO within PLL.
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Kvco2 0 0 0 0 1 1 1 1 Kvco1 0 0 1 1 0 0 1 1 Kvco0 0 1 0 1 0 1 0 1 Fvco 33 MHz 36 MHz 44 MHz 48 MHz 57 MHz 61 MHz 69 MHz 73 MHz Kvco 38MHz/v 38MHz/v 40MHz/v 40MHz/v 63MHz/v 63MHz/v 69MHz/v 69MHz/v
Table 3: Fvco and Kvco settings at 25C
Register0B (PLL_DIV): Address 0Bh
Reset State 12h BIT 7 BIT 6 Unused Ndvsr(6:0) BIT 5 BIT 4 BIT 3 Ndvsr(6:0) BIT 2 BIT 1 BIT 0
(0X0B[6:0])
Represents the divisor. If Nrst{2:0] =0 this register is ignored.
Register0C (PLL_SEQ): Address 0Ch
Reset State 00h BIT 7 BIT 6 Nseq(7:0) BIT 5 BIT 4 BIT 3 Nseq(7:0) BIT 2 BIT 1 BIT 0
(0X0C[7:0])
Represents the divisor sequence.
Register0D (XTAL_BIAS): Address 0Dh
Reset State 48h BIT 7 BIT 6 Xtal(1:0) Xtal(1:0) BIT 5 BIT 4 Reserved BIT 3 BIT 2 BIT 1 Nrst(2:0) BIT 0
Nrst(2:0)
(0X0D[7:6]) Crystal Oscillator bias current selection 00 = Xtal osc. bias current at 120A 01 = Xtal osc. bias current at 180A 10 = Xtal osc. bias current at 270A 11 = Xtal osc. bias current at 450A If OSCIN is used as a Clock input, "00" setting should be used to save power. (0X0D[2:0]) Represents the rate at which the NCO sequence register is reset. The address 0Dh must be the last register to be written to when effecting a change in PLL.
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Register0E (PLL_LOCK): Address 0Eh
Reset State 00h BIT 7 BIT 6 Frcvco PwdnPLL Frcvco BIT 5 LockDet BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 -
PwdnPll LockDet
(0X0E[7]) Force Vco as System clock Enable. 0 = Xtal oscillator as system clock. 1 = forces VCO as system clock. This bit is reset to `0' upon reset, PwdnPll = 1 or ENFE = 0. Both PwdnPll and ENFE are delayed coming out of digital section to keep PLL alive long enough to transition the system clock to crystal clock when Frcvco is reset by PwdnPLL or ENFE. (0X0E[6]) PLL Power down Enable Please refer to the Table 4 Below. 1 = forces Power down of PLL analog section. 0: normal operation (0X0E[5]) PLL Lock indicator. Read only. 1 = PLL locked 0 = PLL not locked. ENFE (Register00 bit7) 0 1 1 PwdnPll (Register0E bit6) X 0 1 Table 4: PLL Power Down PLL PLL Power Off PLL Power On PLL Power Off
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CLOCK GENERATION Crystal Oscillator and Prescaler NCO
The crystal oscillator operates over wide choice of crystals (from 4.9MHz to 27MHz) and it is first input to a Numerically Controlled Oscillator (NCO) -based prescaler (divider) prior to being passed onto an onchip PLL. The intent of the prescaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference frequency, Fref, for the PLL. The NCO prescaler requires a set of three numbers to be entered through the serial port (Pseq[7:0], Prst[2:0] and Pdvsr[2:0]. The PLL also requires 3 numbers as for programming; Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers that control the NCOs, PLLs, and sample rates for the TERIDIAN 73M1903C IC. The tables show some examples of the register settings for different clock and sample rates. A more detailed discussion on how these values are derived can be found in Appendix B.
LockDet 0 Fref NCO prescaler PFD Up Kd Dn Ichp Control 3 Kvco Control NCO FrcVco 3 Charge Pump R1 C1 C2 VCO Kvco Divide by 2/1 1 System Clock
FXtal
Figure 6: Clock Generation
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Reg Address Fs(kHz)
7.2 8.0 2.4*8/7*3 = 8.22857142858 8.4 9.0 9.6 2.4*10/7*3 = 10.2857142857 2.4*8/7*4 = 10.9714285714* 11.2* 12.0 12.8* 2.4*10/7*4 = 13.7142857143 14.4 16.0
Ichp Kvco 8h 9h Ah Bh Ch Dh* (A) [2:0]
DA DA 80 DA DA DA DA 40 54 DA 80 54 DA A4 EF EF F5 EF EF EF EF C7 C7 EF E8 CB EF E9 20 31 41 31 31 32 43 23 23 24 15 26 46 17 13 15 1D 16 18 19 1B 0D 0E 20 11 1A 26 19 10 04 06 14 XX 1A 54 A4 10 XX 0E 0E 14 1A C4 C2 C2 C4 C0 C4 C6 C7 C4 C0 C3 C3 C4 C4 8 10 12 10 10 10 12 8 8 8 6 8 12 6 0 1 1 1 1 2 3 3 3 4 5 6 6 7
Table 7: Clock Generation Register Settings for Fxtal = 27MHz
Reg Address Fs(kHz)
7.2 8.0 2.4*8/7*3 = 8.22857142858 8.4 9.0 9.6 2.4*10/7*3 = 10.2857142857 2.4*8/7*4 = 10.9714285714 11.2 12 12.8 2.4*10/7*4 = 13.7142857143 14.4 16.0
Ichp Kvco 8h 9h Ah Bh Ch Dh* (A) [2:0]
XX XX 0E XX XX XX 04 0E XX XX XX XX XX XX 0A 0A 68 0A 0A 0A 49 68 0A 0A 0A 07 0A 08 10 11 11 21 21 22 23 23 23 14 15 16 26 17 0D 0F 0D 0F 10 12 12 12 15 16 18 12 1B 18 02 XX 02 0E FE XX XX XX XX 02 XX XX XX XX C1 C0 C1 C3 C7 C0 C0 C0 C0 C1 C0 C0 C0 C0 6 6 6 8 8 8 8 8 8 6 6 6 8 6 0 1 1 1 1 2 3 3 3 4 5 6 6 7
Table 8: Clock Generation Register Settings for Fxtal = 24.576MHz
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Reg Address Fs(kHz)
7.2 8.0 8.4 9.0 9.6 2.4*8/7*4 = 10.9714285714 11.2 12 12.8 14.4 16.0
8h
XX XX XX XX XX 02 XX XX XX XX XX
Ichp Kvco 9h Ah Bh Ch Dh* (A) [2:0]
04 04 04 04 04 23 04 04 04 08 03 20 31 31 31 32 33 33 24 35 66 17 0E 10 10 12 13 13 16 18 19 39 18 14 XX 1E XX 10 10 14 XX 1A 1A XX C4 C0 C4 C0 C4 C4 C4 C0 C4 C4 C0 8 10 10 10 10 10 10 8 10 16 6 0 1 1 1 2 3 3 4 5 6 7
Table 9: Clock Generation Register Settings for Fxtal = 9.216MHz
Reg Address Fs(kHz) 7.2 8.0 2.4*8/7*3 = 8.22857142858 8.4 9.0 9.6 2.4*10/7*3 = 10.2857142857 2.4*8/7*4 = 10.9714285714 11.2 12 12.8 2.4*10/7*4 = 13.7142857143 14.4
16.0
8h
Ichp Kvco 9h Ah Bh Ch Dh* (A) [2:0] 15 1A C4 10 13 19 10 C4 10 10 C4 12 6 0 1 1 1 1 2 3 3 3 4 5 6 6
7
DA EF 30 02 2C 31 08 08 72 66 DA EF 41
41 1C 3E C5 12 11 0A 1E C4
DA EF 42 1C 1E C4 12 DA EF 43 1E 7E C6 12 3E A9 08 66 33 14 76 C6 10 6 DA EF 53 DA EF 45 10 8C 46
A4 E9 17
21 1A C4 14 26 20
1C
14 0E 14 C4
14 C4 12 80 C7 12
1E C4 6
54 CA 46 1C 3E C5 12
Table 10: Clock Generation Register Settings for Fxtal = 24.000MHz
Reg Address Fs(kHz) 7.2
16.0
Ichp Kvco 8h 9h Ah Bh Ch Dh* (A) [2:0] 0 92 F4 50 1A 06 C2 14
40 CA 17 1D 02 C1 6 7
Table 11: Clock Generation Register Settings for Fxtal = 25.35MHz
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ANALOG I/O
Figure 7 shows the block diagram of the analog front end. The analog interface circuit uses differential transmit and receive signals to and from the external circuitry. The hybrid driver in the TERIDIAN 73M1903C IC is capable of connecting directly, but not limited to, a transformer-based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA's line coupling transformer and load impedance. The hybrid drivers can also drive high impedance loads without modification. An on-chip band gap voltage is used to provide an internal voltage reference and bias currents for the analog receive and transmit channels. The reference derived from the bandgap, nominally 1.25 Volts, is multiplied to 1.36 Volts and output at the VREF pin. Several voltage references, nominally 1.25 Volts, are used in the analog circuits. The band gap and reference circuits are disabled after a chip reset since the ENFE (Register00 bit7) is reset to a default state of zero. When ENFE=0, the band gap voltage and the analog bias currents are disabled. In this case all of the analog circuits are powered down and draw less than 5 A of current. A clock generator (CKGN) is used to create all of the non-overlapping phase clocks needed for the time sampled switched-capacitor circuits, ASDM, DAC1, and TLPF. The CKGN input is 2 times the analog/digital interface sample rate or 3.072MHz clock for Fs=8kHz.
ANALOG
RXAP
MUX Anti-Alias Filter
AAF
DIGITAL
Decimating Filter Analog Sigma-Delta Modulator
ASDM gain vrefrx rbs MUX 1 rbi t DDEC 15:0
RXAN
SE L
Out
AMUX1 analb
phase clocks (1.536 MHz)
Clocks
PLL/ CLKDIV
VBG
OPSR
BGAP
Bandgap
CKGN
Clock Generator
sck (3.072 MHz)
phase clocks (1.536 MHz)
Serial Port
vreftx
+
SMFLT
TXAP1 TXAN1 TXAP2 TXAN2
Digital Sigma-Delta Modulator DAC
In
Transmit Low Pass Filter
Hybrid Drivers
Outp
tbs
MUX
1 tbit
DSDM
15:0
TLPF
Outn
DAC 1 dtmfbst
analb
txbst
Int Loopbk
DigLoopbk
SFR REGISTERS
Figure 7: Analog block diagram
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MODEM TRANSMITTER
The modem transmitter begins with a 48 tap Transmit Interpolation Filter (TIF) that takes in the 16-bit, two's compliment numbers (TXD) at SDIN pin at Fs=8kHz rate. It up-samples (interpolates) the data to 16kHz rate rejecting the images at multiples of 8kHz that exist in the original TXD data stream and outputs 16-bit, two's compliment numbers to a digital sigma-delta modulator. The gain of the interpolation filter is 0.664 (-3.56dB) at dc. The digital sigma-delta modulator (DSDM) takes 16-bit, two's compliment numbers as input and generates a 1's bit stream which feeds into a D to A converter (DAC1). The gain through DSDM is 1.0. DSDM takes 16-bit, two's compliment numbers as input and generates a 1's bit stream that feeds into a D to A converter (DAC1). DAC1 consists of a 5-tap FIR filter and a first order switched capacitor low pass filter both operating at 1.536MHz. It possesses nulls at multiples of 384kHz to allow decimation by the succeeding filter. DAC1's differential output is fed to a 3rd-order switched-capacitor low pass filter (TLPF). The output of TLPF drives a continuous time smoothing filter. The sampling nature of the transmitter leads to an additional filter response that affects the in-band signals. The response is in the form of sin(x)/x and can be expressed as 20*log [(sin(PI*f/fs))/(PI*f/fs)] where f = signal frequency and fs = sample frequency = 16 kHz. Figure 8 and Figure 9 shows the frequency response of the transmit path from TXD to TXAP/TXAN. The transmit bandwidth is about 3.65kHz when Fs=8kHz. The bandwidth scales with Fs, the sampling rate. In case of Fs=9.6kHz , then the bandwidth is 3.65kHz x 9.6/8 = 4.38kHz and Fs=10.28kHz, the bandwidth is 3.65kHz x 10.28/8 = 4.69kHz. This is applicable for both transmit and receive path filters.
Figure 8: Overall TX path frequency response at 8kHz sample rate
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Figure 9: Frequency response of TX path for DC to 4kHz in band signal at 8kHz sample rate
TRANSMIT LEVELS
The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF) has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will result in a 0.5 (-6dB) gain change in the analog output signal. The following formula describes the relationship between the transmit code word and the output level at the transmit pins (TXAP/TXAN): Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr Vout is the differential peak voltage at the TXAP and TXAN pins. Code is the 16-bit, two's compliment transmit code word written out by the DSP to the DSDM (via TIF). The code word falls within a range of 32,767. For a sinusoidal waveform, the peak code word should be used in the formula to obtain the peak output voltage. DSDMgain is the scaling factor used on the transmit code word to reduce the possibility of saturating the modulator. This value is set to 0.640625(-3.555821dB) at dc in the 48 tap transmit interpolation filter (TIF) that precedes DSDM. dacGAIN is the gain of the DAC. The value dacGAIN is calculated based on capacitor values inside DAC1 and dacGAIN=8/9=0.8889. The number 32,767 refers to the code word that generates an 82% "1's" pulse density at the output of the DSDM. As can be seen from the formula, the D to A conversion is dependent on the level of VREF. Also when DTMFBST bit is set, VREF is increased from 1.36V to
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1.586V to allow higher transmit level or 16.6% increase in gain. This bit is intended for enhancing the DTMF transmit level and should not be used in data mode. TLPFgain is the gain of TLPF and nominally equals to 0.00dB or 1.0. SMFLTgain is the gain of SMFLT and nominally equal to 1.445 or 3.2dB. When TXBST0 bit is set, the gain is further increased by 1.65dB (1.21) for the total of 4.85 dB. This is to accommodate greater hybrid insertion loss encountered in some applications. FreqFctr shows dependency of the entire transmit path on frequency. See Figure 8. With the transmit code word of +/- 32,767, the nominal differential swing at the transmit pins at dc is: Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr = 2 * 32,767/32767 * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.0 = 2.31Vpk diff. When DTMFBST bit is set, Vout (V) = 1.166 * 2.31= 2.693Vpk diff. When TXBST0 bit is set, Vout (V) = 1.21 * 2.31= 2.795Vpk diff. (1) When both DTMFBST and TXBST0 are set to 1, Vout (V) = 2.795 * 1.166 = 3.259Vpk diff. [1] If not limited by power supply or internal reference.
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TRANSMIT POWER - dBm
To calculate the analog output power, the peak voltage must be calculated and the peak to rms ratio (crest factor) must be known. The following formula can be used to calculate the output power, in dBm referenced to 600. Pout (dBm) = 10 * log [ ( Vout (V) / cf )2 / ( 0.001 * 600 ) ] The following example demonstrates the calculation of the analog output power given a 1.2kHz FSK tone (sine wave) with a peak code word value of 11,878 sent out by the DSP. The differential output voltage at TXAP-TXAN will be: With FreqFctr = 1.02, (See Figure 8) Vout (V) = 2 * (11,878/32,767) * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.02 = 0.841Vpk. The output signal power will be: Pout (dBm) = 10 * log [(0.841 / 1.41)2 / (0.001 * 600) ] = - 2.29dBm. Transmit Type crest factor Max line level V.90 4.0 -12dBm QAM 2.31 -9dBm DPSK 1.81 -9dBm FSK 1.41 -9dBm DTMF 1.99 -5.7dBm Table 13: Peak to RMS ratios and maximum transmit levels for various modulation types
MODEM RECEIVER
A differential receive signal applied at the RXAP and RXAN pins or the output signal at TXAP and TXAN pass through a multiplexer, which selects the inputs to the ADC. In normal operation, RXAP/RXAN are selected. In analog loopback mode, TXAP/TXAN are selected. The DC bias for the RXAP/RXAN inputs is supplied from TXAP/TXAN thru the external DAA in normal conditions. It can be supplied internally, in the absence of the external DAA, by setting RXPULL bit in Register02. The output of the multiplexer goes into a second-order continuous time, Sallen-Key, low-pass filter (AAF) with a 3dB point at approximately 40kHz. The filtered output signal is the input to an analog sigma-delta modulator (ASDM), clocked at an over sampling frequency of 1.536MHz for Fs = 8kHz, which converts the analog signal to a serial bit stream with a pulse density that is proportional to the amplitude of the analog input signal. There are three gain control bits for the receive path. The RXGAIN bit in control register one results in a +20dB gain of the receive signal when set to a "1". This 20dB of gain compensates for the loss through the DAA while on hook. It is used for Caller ID reception. This gain is realized in the front end of ASDM.
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The other gain bits in control register 1, RXG1:0, compensate for differences in loss through the receive path.
RXG1
0 0 1 1
RXG0
0 1 0 1
Receive Gain Setting
6dB 9dB 12dB 0dB
Table 12: Receive Gain The output of ASDM is a serial bit stream that feeds multiple digital sinc3 filters. The filters are synchronized so that there is one sample available after every 96 analog samples or at a rate of 16kHz for Fs=8kHz. The output of the sinc3 filter is a 17 bit, two's compliment number representing the amplitude of the input signal. The sinc3 filter, by virtue of holding action (for 96 sample period), introduces a droop in the passband that is later corrected for by a 48-tap FIR filter that follows. The output of the sinc3 filter is input to another 48 tap digital FIR filter that provides an amplitude correction as well as rejecting noise above Fs/2 or 4kHz for Fs=8kHz. The output of this filter is then decimated by a factor of 2; so, the final output is 16 bit, two's compliment samples at a rate of 8 kHz. Figure 10 and Figure 11 depict the sinc3 filter's frequency response of ASDM along with the 48 tap digital FIR response that compensates for it and the resulting overall response of the receiver.
Figure 10: Overall receiver frequency response at 8kHz sample rate
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Figure 11: Rx passband response at 8kHz sample rate It is important to keep in mind that the receive signal should not exceed 1.16Vpk-diff for proper performance for Rxg=11 (0dB). In particular, if the input level exceeds a value such that one's density of RBS exceeds 99.5%, sinc3 filter output will exceed the maximum input range of the decimation filter and consequently the data will be corrupted. Also for stability reasons, the receive signal should not exceed 1.16Vpk differentially. This value is set at around 65% of the full receive signal of 1.791Vpkdiff at RXAP/RXAN pins that "would" corresponds to ASDM putting out all ones. Figure 12 and Figure 13 show the spectrum of 1kHz tone received at RXAP/RXAN of 1.16Vpk-diff and 0.5kHz and 1.0kHz tones of 0.6Vpk-diff each, respectively for Fs=8kHz. Note the effect of FIR suppressing the noise above 4kHz but at the same time enhancing (in order to compensate for the passband droop of sinc3 filter) it near the passband edge of 4kHz. The bandwidth of the receive filter is about 3.585kHz when Fs=8kHz. The bandwidth scales with Fs, the sampling rate. Please refer to the MODEM TRANSMITTER section for more information.
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Figure 12: RXD Spectrum of 1kHz tone
Figure 13: RXD Spectrum of 0.5kHz, 1kHz, 2kHz, 3kHz and 3.5kHz tones of Equal Amplitudes
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TEST MODES
There are two loop back test modes that affect the configuration of the analog front end. The internal loop back mode connects the serial bit stream generated by the analog receiver to the input of the analog transmitter. This loop back mode is similar to a remote analog loop back mode and can be used to evaluate the operation of the analog circuits. When using this loop back mode, the TXAN/TXAP pins should not be externally coupled to the RXAP/RXAN pins. Set bit 4 (INTLB) in register 01h (CTRL2) to enter this loop back mode. The second loop back test mode is the external loop back mode, or local analog loop back mode. In this mode, the analog transmitter outputs are fed back into the input of the analog receiver. Set bit 5 (ANALB) in register 01h (CTRL2) to enter this loop back mode. In this mode, TBS must be kept to below a value that corresponds to less than 1.16V/2.31V x -6dB = 25% of the full scale code of +/- 32768 at TXD in order to ensure that the receiver is not overdriven beyond the maximum of 1.16Vpkpk diff for Rxg=11(0dB) setting. See Table 16 on page 32 for the maximum allowed transmit levels. Check the transmitted data against received data via serial interface. This tests the functionality of essentially all blocks, both digital and analog, of the chip. There is a third loopback mode that bypasses the analog circuits entirely. Digital loop back forces the transmitter digital serial bit stream (from DSDM) to be routed into the digital receiver's sinc3 filters. Set bit 6 (DIGLB) in register 01h (CTRL2) to enter this loop back mode.
POWER SAVING MODES
The 73M1903C has only one power conservation mode. When the ENFE, bit 7 in register 00h, is zero the clocks to the filters and the analog are turned off. The transmit pins output a nominal 80k impedance. The clock to the serial port is running and the GPIO and other registers can be read or updated.
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device. PARAMETER Supply Voltage Pin Input Voltage (except OSCIN) Pin Input Voltage (OSCIN) RATING -0.5V to +4.0V -0.5V to 6.0V -0.5V to VDD + 0.5V
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage (VDD) with respect to VSS Oscillator Frequency Operating Temperature RATING 3.0V to 3.6V 24.576 MHz 100ppm -40C to +85C
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DIGITAL SPECIFICATIONS DC CHARACTERISTICS
PARAMETER Input Low Voltage Input High Voltage (Except OSCIN) Input High Voltage OSCIN Output Low Voltage (Except OSCOUT, FS, SCLK, SDOUT) Output Low Voltage OSCOUT Output Low Voltage FS,SCLK,SDOUT Output High Voltage (Except OSCOUT, FS, SCLK, SDOUT) Output High Voltage OSCOUT Output High Voltage FS,SCLK,SDOUT Input Low Leakage Current (Except OSCIN) Input High Leakage Current (Except OSCIN) Input Leakage Current OSCIN Input High Leakage Current OSCIN Condition VIL VIH1 VIH2 VOL VOLOSC VOL VOH VOHOSC VOH IIL1 IIH1 IIL2 IIH2 IOL = 4mA IOL = 3.0mA IOL = 1mA IOH = -4mA IOH =-3.0mA IOH = -1mA VSS < Vin < VIL1 VIH1 < Vin < 5.5 VSS < Vin < VIL2 VIH2 < Vin < VDD 1 1 VDD - 0.45 VDD - 0.9 VDD - 0.45 1 1 30 30 MIN -0.5 0.7 VDD 0.7 VDD NOM MAX 0.2 * VDD 5.5 VDD + 0.5 0.45 0.7 0.45 UNIT V V V V V V V V V A A A A
IDD current at 3.0V - 3.6V Nominal at 3.3V IDD Total current Fs=8kHz, IDD Xtal=27MHz IDD Total current Fs=11.2kHz, IDD Xtal=27MHz IDD Total current Fs=14.4kHz, IDD Xtal=27MHz IDD Total current Fs=16.0kHz, IDD Xtal=27MHz IDD Total current IDD ENFE=0
9 10.3 11.8 12.2 2
12.0 13.4 14.5 16.0 2.5
mA mA mA mA mA
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AC TIMING
PARAMETER SCLK Period (Tsclk) (Fs=8kHz) SCLK to FS Delay (td1) SCLK to FS Delay (td2) SCLK to SDOUT Delay (td3) (With 10pf load) Setup Time SDIN to SCLK (tsu) Hold Time SDIN to SCLK (th) MIN 15 10 NOM 1/2.048MHz -MAX 20 20 20 UNIT ns ns ns ns ns ns
Table 14: -Serial interface Timing
td1
td2
tclk
SCLK
FS
SDOUT
RX15
RX14
RX1
RX0
td3 tsu
SDIN
TX15
TX14
TX
TX0
th
Figure 14: Serial Port Data Timing
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ANALOG SPECIFICATIONS DC SPECIFICATIONS
VREF is not brought out to a pin on the 73M1903C. This specification is for information only. The VREF voltage may be measured as the quiescent DC level at the transmit pins. Parameter VREF VREF Noise VREF PSRR Test Condition VDD= 3.0V - 3.6V. 300Hz-3.3kHz 300Hz-30kHz Min Nom 1.36 -86 Max -80 Units V dBm600 dB
40*
Table 15: Reference Voltage Specifications
AC SPECIFICATIONS
The table below shows the maximum transmit levels that the output drivers can deliver before distortion through the DAA starts to become significant. The loss though the DAA transmit path is assumed to be 7 dB. The signals presented at TXAP and TXAN are symmetrical. The transmit levels can be increased by setting either TXBST0 (+1.5dB) or/and DTMFBST (+0.83dB) for the combined total gain of 2.33dB. These can be used where higher-level DTMF tones are required.
MAXIMUM TRANSMIT LEVELS
Transmit Type VPA=2.7V to 3.6V; All rms and peak voltages are relative to VREF -12.0 -11.0 4 V.90 QAM -7.3 -6.3 2.31 DPSK FSK DTMF (high tone) DTMF (low tone) -5.1 -3.0 -7.8 -9.8 -4.1 -2.0 -6.8 -8.8 1.81 1.41 1.41 1.41 Maximum Maximum singleSingle-ended rms Single-ended differential line ended level at peak to Voltage at TXA Peak Voltage at level (dBm0) TXA pins (dBm) rms ratio pins (V) TXA pins (V) 0.2175 0.377 0.481 0.617 0.354 0.283 0.87 0.87 0.87 0.87 0.500 0.400
Table 16: Maximum Transmit Levels
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PERFORMANCE Receiver
Parameter Input Impedance Test Conditions Measured at RXAP/N relative to VREF RXPULL=HI Measured at RXAP/N relative to VREF RXPULL=LO Rxgain = 1; 1kHz; RXAP/N=0.116Vpk-diff Gain Measured relative to Rxgain=0 RXGAIN=1 for Fs=8kHz RXGAIN =1 for Fs=12kHz RXGAIN =1 for Fs=14.4kHz THD = 2nd and 3rd harmonic. RXGAIN =1 Gain Measured relative to RXG[1:0]=11 (0dB) @1 kHz RXG[1:0]=00 RXG[1:0]=01 RXG[1:0]=10 Input 1.16Vpk-diff at RXA. Measure gain at 0.5kHz, and 2kHz. Normalized to 1kHz. Gain at 0.5kHz Gain at 1kHz (Normalized) Gain at 2.0kHz Short RXAP to RXAN. Measure input voltage relative to VREF Normalized to VBG=1.25V. Includes the effect of AAF(-0.4dB) with Bits 1,0 of CTRL2 register (01h) = 00. Peak voltage measured differentially across RXAP/RXAN. 1kHz 1.16Vpk-diff at RXA with Rxg=11 THD = 2nd and 3rd harmonic. 80 85 DB Min Nom 230 1.0 17.0 16.2 15.7 64 5.8 8.8 11.8 -0.29 -0.2 -30 18.5 17.4 17.2 70 6 9 12 -0.042 0.000 -0.06 0 41 1.16 6.2 9.2 12.2 0.21 0.2 30 dB dB dB dB dB dB MV V/bit Vpk-diff 20.0 18.7 18.7 Max Units k M dB dB dB
Receive Gain Boost
Total Harmonic Distortion (THD) RXG Gain
Passband Gain
Input offset Sigma-Delta ADC Modulation gain Maximum Analog Signal Level at RXAP/RXAN Total Harmonic Distortion (THD) Noise
Transmit V.22bis low band; FFT run on ADC samples. Noise in 0 to 4kHz band -85 -80 DBm 0dBm 1000Hz sine wave at TXAP; FFT Crosstalk on Rx ADC samples, 1st four harmonics -100 DB Reflected back to receiver inputs. Note: RXG[1:0] and RXGAIN are assumed to have settings of `0' unless they are specified otherwise. Table 17: Receiver Performance Specifications
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Transmitter
Parameter DAC gain (Transmit Path Gain) DC offset - Differential Mode DC offset - Common Mode TXBST0 Gain DTMFBST Gain Total Harmonic Distortion (THD) Test Condition Code word of 32,767 @1kHz; TXBST0=0; DTMFBST=0 Across TXAP and TXAN for DAC input = 0 Average of TXAP and TXAN for DAC input = 0; relative to VREF Code word of 32,767 @1kHz; relative to TXBST0=0; TXBST1=0 Code word of 32,767 @1kHz; relative to TXBST0=0; TXBST1=0 Code word of 24,575 (75% scale) @1kHz; relative to TXBST0=0;TXBST1=0 THD = 2nd and 3rd harmonic. Code word of 26,213 (80% scale) @1kHz; relative to TXBST0=0;TXBST1=0 THD = 2nd and 3rd harmonic. Code word of 29,490 (90% scale) @1kHz; relative to TXBST0=1;TXBST1=1 THD = 2nd and 3rd harmonic. Code word of 29,490(90% scale) @1kHz; relative to TXBST0=1;DTMFBST=1 THD = 2nd and 3rd harmonic At output (TXAP-TXAN): DTMF 1.0kHz, 1.2kHz sine waves, summed 2.0Vpk (-2dBm tone summed with 0dBm tone) Refer to TBR 21 specifications for description of complete requirements. 200Hz - 4.0kHz -30 dBm signal at VPA 300Hz - 30kHz 300Hz - 3.2kHz Code word of 32,767 @1kHz. Measure gain at 0.5kHz, and 2kHz relative to 1kHz. Gain at 0.5kHz Gain at 1kHz (Normalized) Gain at 2.0kHz Gain at 3.3kHz Min Nom 70 -100 -80 1.65 1.335 -80 -85 100 80 Max Units v/bit MV MV DB DB32 dB dB dB dB dB below low tone V 40 -0.125 0.125 dB dB
-75 -60
-85 -70 -70
1200 Resistor across TNAN/TXAP
Intermod Distortion
70
Idle Channel Noise PSRR Passband Ripple
110
Transmit Gain Flatness
0.17 0 0.193 -0.12
dB dB dB dB
Table 18: Transmitter Performance Specifications
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Parameter Test Condition Min Nom Max Units
TXAP/N output TXDIS =1. impedance Measure impedance differentially differentially between TXAP and TXAN. (TXDIS=1) 160 k Txap/n common TXDIS=1 output offset Short TXAP and TXAN. Measure the -20 0 20 mV (TXDIS=1) voltage respect to Vbg Note: TXBST0 and DTMFBS are assumed have setting 0's unless they are specified otherwise. Table 19: Transmitter Performance Specifications (continued)
PACKAGE OPTIONS (Drawings not to scale)
SckMode SDOUT GPIO7 GPIO6 TYPE SDIN RST 26 VPD 25
32
31
30
29
28
VND VPD GPIO0 GPIO1 GPIO2 GPIO3 FS SCLK
27
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22
GPIO5 GPIO4 VND FSD VPPLL OSCIN OSCOUT VNPLL
TERIDIAN 73M1903C
21 20 19 18 17
TXAN1
TXAN2
TXAP2
TXAP1
RXAN
RXAP
VPA
73M1903C QFN 32
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VNA
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MECHANICAL DRAWIN
5 2.5
0 .8 5 N O M ./ 0 .9 M A X . 0 .0 0 / 0 .0 0 5 0 .2 0 R E F .
1 2 3
2.5 5
S E A T IN G PLANE
TOP VIEW
0.35 / 0.45
S ID E V IE W
3.0 / 3.75 0.18 / 0.3 1.5 / 1.875
CHAMFERED 0.30
1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.2 MIN. 0.35 / 0.45 0.5 0.5 0.25
BOTTOM VIEW
32 pin QFN Controlling dimensions in mm
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APPENDIX A 73M1903C DAA Resistor Calculation Guide
TXAP1 R1 RW CBlock Bridge Diode Hook Switch RING DETECTOR Bead RING Bead
ACTIVE INDUCTOR TXAN1 R1
TIP
C1 R3 RXAP R2
C1
R3 RXAN R2
Figure 15: Typical DAA block diagram The following procedure can be used to approximate the component values for the DAA. The optimal values will be somewhat different due to the effects of the reactive components in the DAA (this is a DC approximation). Simulations with the reactive components accurately modeled will yield optimal values. The procedures for calculating the component values in the DAA are as follows. First determine R1. For a differential transmitter R1 is composed of 2 resistors that represent the difference in resistance between the total winding resistance of the transformer and the reflected impedance, 600 . This value is usually supplied by the transformer vendor. The DAA should be designed to reflect 600 when looking in at TIP/RING. The transformer is normally a 1 to 1 turns ratio, the holding coil and ring detect circuit are high impedance, and Cblock is a high value so in the frequency band of interest it is negligible. The sum of R2 and R3 is much greater than R1, and the output impedance of the drivers driving TXAP/TXAN are low, therefore: Rin 2 . R1 RW Rohswitch 2 . Rbead RW is the sum of the winding resistance of both sides of the transformer. Measure each side of the transformer with an Ohmmeter and sum them. Rohswitch is the on resistance of the Off Hook Switch. Mechanical Relay switches can be ignored, but Solid State Relays sometimes have an appreciable on resistance. Rbead is the DC resistance of whatever series RF blocking devices may be in the design. For Rin equal to 600 : 600 RW Rohswitch 2 . Rbead R1 2 To maximize THL (Trans-Hybrid Loss), or to minimize the amount of transmit signal that shows up back on the Receive pins. The RXAP/RXAN pins get their DC bias from the TXAP/TXAN pins. By capacitively coupling the R3 resistors with the C1 caps, the DC offset can be minimized from the TXAP/TXAN to the RXAP/RXAN because the DC offset will be divided by the ratio of the R1 resistors to the winding resistance on the modem side of the transformer.
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Next make the sum of R2 + R3 much higher than 600 . Make sure they are lower than the input impedance of the RXAP/RXAN pins; otherwise they can move the frequency response of the input filter. So let R2 + R3 = 100 K. 100 K R3 Rwtot 600 1 1200 where
Rwtot RW Rohswitch 2 . Rbead R2 100 K R3 Use 1% resistors for R1, R2, and R3 To select the value for C1, make the zero at around 10Hz. 1 10 2 . . 100 K . C1 1 . . 100 K . 10 2 C1 0.15 uF C1
The blocking cap Cblock should also have the same frequency response, but due to the low impedance, its value will be much higher, usually requiring a polarized cap. A blocking cap may also be needed on the modem side of the transformer if the DC offset current of the transmit pins will exceed the current rating of the transformer. 1 Cblock 2 . . 600. 10 Cblock 27 uF When using a wet transformer design as in the following Figure 16, the only difference is that the
Hook Switch RING DETECTOR TXAN1 R1 Bead
TXAP1
R1
RW
TIP
Bead
RING
C1 R3 R2 RXAP R3 RXAN R2
C1
Figure 16: Single transmitter arrangement
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blocking capacitor, Cblock, it is removed. All other equations still hold true. When both drivers are used for worldwide application, the recommended connections are shown below. The termination realized when the primary driver is selected is 2R1 + Rwtot; With the secondary driver is selected it is 2Z4 + Rwtot.
R1 RW
TXAP1 TXAN1 TXAP2 TXAN2
R1 Z4 Z4 ZL
C1 R3 RXAP R3 R2 R3 RXAN R3 R2
Figure 17: Dual transmitter arrangement Still keep R2 + R3 = 100K. 100K R3 Rwtot + 600 1+ Rwtot + 600 + 1200 and
R2 100 K R3.
Trans-Hybrid Loss (THL)
Trans-Hybrid Loss is by definition the loss of transmit signal from Tip/Ring to the receive inputs on the modem IC. This definition is only valid when driving a specific phone line impedance. In reality, phone line impedances are never perfect, so this definition isn't of much help. Instead, as an alternate definition that helps in analysis for this modem design, THL is the loss from the transmit pins to the receive pins. In this definition the worst-case THL from the transmit pins to the Receive pins is 10.8dB. An insertion loss of 7dB is assumed accounting for losses due to switch, bridge and transformer.
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APPENDIX B Crystal Oscillator
The crystal oscillator is designed to operate over wide choice of crystals (from 4.9MHz to 27MHz). The crystal oscillator output is input to an NCO based pre-scaler (divider) prior to being passed onto an onchip PLL. The intent of the pre-scaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference frequency, Fref, for the PLL. A set of three numbers- Pdvsr (5 bit), Prst (3 bit) and Pseq (8 bit) must be entered thru the serial port as follows: Pdvsr = Integer [Fref/Fxtal]; Prst = Denominator of the ratio (Fref/Fxtal) minus 1 when it is expressed as a ratio of two smallest integers = Nnco1/Dnco1; Pseq = Divide Sequence
Fxtal Pdvsr Pdvsr +1
Sequence Register
mux
overflow
Fref
Counter
count ctrl
Sequence Counter
Rst Pseq[7:0] Prst[2:0]
Figure 18: NCO block diagram
Please note that in all cases, pre-scaler should be designed such that pre-scaler output frequency, Fref, is in the range of 2 ~ 4MHz. In the first example below, the exact divide ratio required is Fxtal/Fref = 15.625 =125/8. If a divide sequence of {/16,/16,/15,/16,/16,/15,/16,/15} is repeated, the effective divide ratio would be exactly 15.625. Consequently, Pdvsr of 15, the length of the repeating pattern, Prst = 8 -1 =7, and the pattern, {1,1,0,1,1,0,1,0}, where 0 means Pdvsr, or /15, and 1 means Pdvsr +1, or /16 must be entered as below. Example 1: Fxtal = 27MHz, Fref = 1.728MHz. Pdvsr = Integer [Fxtal/Fref] = 15 =0Fh Prst[2:0] = 8 - 1 = 7 from Fxtal/Fref = 15.625 =125/8; Pseq = /16,/16,/15,/16,/16,/15,/16,/15 => {1,1,0,1,1,0,1,0} =DAh. In the second example, Fxtal/Fref =4.0. This is a constant divide by 4. Thus Pdvsr is 4, Prst = 1 -1 =0 and Pseq = {x,x,x,x,x,x,x,x).
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Example 2: Fxtal = 18.432MHz, Fref = 2.304 MHz. Pdvsr = Integer [Fxtal/Fref] = 8 = 8h; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 18.432/2.304 = 8/1; Pseq = {x,x,x,x,x,x,x,x} = xxh Example 3: Fxtal = 24.576MHz, Fref = 2.4576MHz. Pdvsr = Integer [ Fxtal/Fref] = 10 = Ah; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/2.4576 = 10/1; Pseq = {x,x,x,x,x,x,x,x} = xxh Example 4: Fxtal = 24.576MHz, Fref = 3.072MHz. Pdvsr = Integer [ Fxtal/Fref] = 8 = 8h; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/3.072 = 8/1; Pseq = {x,x,x,x,x,x,x,x} = xxh It is also important to note that when Fxtal/Fref is an integer the output of the prescaler is a straight frequency divider (example 2). As such there will be no jitter generated at Fref. However if Fxtal/Fref is a fractional number, Fref, at the output of the prescaler NCO would be exact only in an average sense (example 1) and there will be a certain amount of fixed pattern (repeating) jitter associated with Fref which can be filtered out by the PLL that follows by appropriately programming the PLL. It is important to note, however, that the fixed pattern jitter does not degrade the performance of the sigma delta modulators so long as its frequency is >> 4kHz.
PLL
NCO Prescaler Up Fref PFD Kd Dn Ichp Control 3 Kvco Control NCO Charge Pump R1 C1 C2 VCO Kvco Divide by 2/1
3
Figure 19: PLL Block Diagram 73M1903C has a built in PLL circuit to allow an operation over wide range of Fs. It is of a conventional design with the exception of an NCO based feedback divider. (See Figure 18: PLL Block Diagram). The architecture of the 73M1903C dictates that the PLL output frequency, Fvco, be related to the sampling rate, Fs, by Fvco = 2 x 2304 x Fs. The NCO must function as a divider whose divide ratio equals Fref/Fvco. Just as in the NCO prescaler, a set of three numbers- Ndvsr ( 7 bits ), Nrst ( 3 bits ) and Nseq ( 8 bits ) must be entered thru a serial port to affect this divide: Ndvsr = Integer [Fref/Fxtal] ; Nrst = Denominator of the ratio (Fvco/Fref), Dnco1, minus 1, when it is expressed as a ratio of two smallest integers = Nnco1/Dnco1; Nseq = Divide Sequence
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Example 1: Fs = 7.2kHz or Fvco = 2 x 2304 x 7.2kHz =33.1776MHz, Fref = 1.728MHz. Ndvsr = Integer [ Fvco/Fref ] = 19 Nrst = 5 - 1 = 4 from Fvco/Fref = 19.2 = 96/5; Nseq = /19, /19, /19, /19, /20 => {0,0,0,0,1} =xxx00001 = 01h. Example 2: Fs = 8.0kHz or Fvco = 2 x 2304 x 8kHz =36.864MHz, Fref = 2.304MHz. Ndvsr = Integer [Fvco/Fref] = 16 = 10h; Nrst= 1-1 = 0 from Fvco/Fref = 16/1; Nseq = {x,x,x,x,x,x,x,x} = xxh. Example 3: Fs = 9.6kHz or Fvco = 2 x 2304 x 9.6kHz =44.2368MHz, Fref = 2.4576MHz. Ndvsr = Integer [Fvco/Fref] = 18 = 16h; Nrst= 1-1 = 0 from Fvco/Fref = 18/1; Nseq = {x,x,x,x,x,x,x,x} = xxh. Example 4: Fs = 16.0kHz or Fvco = 2 x 2304 x 16.0kHz =73.728MHz, Fref = 3.072MHz. Ndvsr = Integer [Fvco/Fref] = 24 =18h; Nrst= 1-1 = 0 from Fvco/Fref = 24/1; Nseq = {x,x,x,x,x,x,x,x} = xxh. It is important to note that in general the NCO based feedback divider will generate a fixed jitter pattern whose frequency components are at Fref/Accreset2 and its integer multiples. The overall jitter frequency will be a nonlinear combination of jitters from both pre-scaler and PLL NCO. The fundamental frequency component of this jitter is at Fref/Prst/Nrst. The PLL parameters should be selected to remove this jitter. Three separate controls are provided to fine tune the PLL as shown in the following sections. To ensure quick settling of PLL, a feature was designed into the 73M1903C where Ichp is kept at a higher value until LockDet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus PLL is guaranteed to have the settling time of less than one Frame Synch period after a new set of NCO parameters had been written to the appropriate registers. The serial port register writes for a particular sample rate should be done in sequence starting from register 08h ending in register 0Dh. 0Dh register should be the last one to be written to. This will be followed by a write to the next register in sequence (0Eh) to force the transition of Sysclk from Xtal to Pllclk. Upon the system reset, the system clock is reset to Fxtal/9. The system clock will remain at Fxtal/9 until the Host forces the transition, but no sooner the second Frame Synch period after the write to 0Dh. When this happens, the system clock will transition to PLLclk without any glitches thru a specially designed deglitch MUX.
Examples of NCO settings Example 1:
Crystal Frequency = 24.576MHz; Desired Sampling Rate, Fs = 13.714kHz(=2.4kHz x 10/7 x 4) Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4kHz x 10/7 x 4 = 13.714kHz, or Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 10/7 x 4 = 63.19543MHz.
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Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by :
Fvco / Fxtal
=
2 * 2304 * 2.4kHz * 10/7 * 4 24.576MHz
.
After a few rounds of simplification this ratio reduces to:
Fvco / Fxtal = 18 7 Nnco1 Dnco1 Nnco2 Dnco2 =( 1 7 = )*( 1 7 1 18 18 1 )
=
, where Nnco1 and Nnco2 must be < or equal to 8. The ratio, Nnco1/Dnco1 = 1/7, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 = 1/18 for the NCO in the PLL. Prescaler NCO: From Nnco1/Dnco1 = 1/7, Pdvsr = Integer [nco1/Nnco1] = 7; Prst[2:0] = Nnco1 - 1 = 0; this means NO fractional divide. It always does /7. Thus Pseq becomes "don't care" and is ignored. Pseq = {x,x,x,x,x,x,x,x} = xxh. PLL NCO: From Nnco2/Dnco2 = 1/18, Ndvsr = Integer [Dnco2/Nnco2] = 18; Nrst[2:0] = Nnco2 - 1 = 0; this means NO fractional divide. It always does /18. Thus Pseq becomes "don't care" and is ignored. Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example 2:
Crystal Frequency = 24.576MHz; Desired Sampling Rate, Fs = 10.971kHz=2.4kHz x 8/7 x4 Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4kHz x 8/7 x 4 =10.971kHz. Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 8/7 x 4 = 50.55634MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by :
Fvco / Fxtal
=
2 * 2304 * 2.4kHz * 8/7 * 4 24.576MHz
.
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After a few rounds of simplification this ratio reduces to: 4 18 Fvco / Fxtal = ( )*( ) 35 1 Nnco1 4 Dnco1 35 = = Nnco2 1 Dnco2 18 , where Nnco1 and Nnco2 must be < or equal to 8. The ratio, Nnco1/Dnco1 = 4/35, is used to form a divide ratio for the NCO in pre-scaler and Nnco2/Dnco2 =1/18 for the NCO in the PLL. Pre-scaler NCO: From Nnco1/Dnco1 = 4/35, Pdvsr = Integer [ Dnco1/Nnco1 ] = 8; Prst[2:0] = Nnco1 - 1 = 3; Dnco1/Nnco1 = 35/4 = 8.75 suggests a divide sequence of {/9,/9,/9,/8}, or Pseq = {x,x,x,x,1,1,1,0} = xDh. PLL NCO: From Nnco2/Dnco2 = 1/18, Ndvsr = Integer [ Dnco2/Nnco2 ] = 18; Nrst[2:0] = Nnco2 - 1 = 0; this means NO fractional divide. It always does /18. Thus Pseq becomes "don't care". Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example3:
Crystal Frequency = 27MHz; Desired Sampling Rate, Fs = 7.2kHz Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4kHz x 3 = 7.2kHz. Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 3 = 33.1776MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by :
Fvco / Fxtal
Fvco / Fxtal =(
=
8 125 Nnco1 Dnco1 Nnco2 Dnco2
2 * 2304 * 2.4kHz * 3 27MHz
)*( 96 5 = ) 8 125 5 96
.
After a few rounds of simplification this reduces to: .
=
The two ratios are not unique and many other possibilities exist. But for this particular application, they are found to be the best set of choices within the constraints of Prst and Nrst allowed. (Nnco1, Nnco2 must be less than or equal to 8.)
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The ratio, Nnco1/Dnco1 = 8/125, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 =5/96 for the NCO in the PLL. Pre-scaler NCO: From Nnco1/Dnco1 = 8/125, Pdvsr = Integer [ Dnco1/Nnco1 ] = 15; Prst[2:0] = Nnco1 - 1 = 7; Dnco1/Nnco1 = 125/8 = 15.625 suggests a divide sequence of {/16,/16,/15,/16,/16,/15,/16,/15}, or Pseq = {1,1,0,1,1,0,1,0} = DAh. PLL NCO: From Nnco2/Dnco2 = 5/96, Ndvsr = Integer [ Dnco2/Nnco2 ] = 19; Nrst[2:0] = Nnco2 - 1 = 4; Dnco2/Nnco2 = 19.2 suggests a divide sequence of {/19, /19, /19, /19, /20}, or Nseq = {x,x,x,0,0,0,0,1} = x1h.
Example4:
Crystal Frequency = 24.576MHz; Desired Sampling Rate, Fs = 16.0kHz Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4kHz x 20/3 = 16.0kHz. Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 20/3 = 73.728MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by :
Fvco / Fxtal
Fvco / Fxtal =(
=
24 1 Nnco1 Dnco1 Nnco2 Dnco2
2 * 2304 * 2.4kHz * 20/3 24.576MHz
)*( 1 8 = ) 1 8 1 24
.
After a few rounds of simplification this reduces to:
=
The ratio, Nnco1/Dnco1 = 1/1, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 =1/24 for the NCO in the PLL. Pre-scaler NCO: From Nnco1/Dnco1 = 1/8, Pdvsr = Integer [ Dnco1/Nnco1 ] = 8 = 08h, Prst[2:0] = Nnco1 - 1 = 0; this means NO fractional divide. It always does /8. Thus Pseq becomes "don't care". Pseq = {x,x,x,x,x,x,x,x}= xxh. PLL NCO: From Nnco2/Dnco2 = 1/24, Ndvsr = Integer [ Dnco2/Nnco2 ] = 24 = 18h, Nrst[2:0] = Nnco2 - 1 = 0; this means NO fractional divide. It always does /24. Thus Nseq becomes "don't care". Nseq = {x,x,x,x,x,x,x,x} = xxh.
Page: 45 of 46
(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
73M1903C Modem Analog Front End
DATA SHEET
ORDERING INFORMATION
PART DESCRIPTION 73M1903C 32-Lead QFN Lead Free 73M1903C 32-Lead QFN Lead Free, Tape and Reel ORDER NUMBER 73M1903C-IM/F 73M1903C-IMR/F
Data Sheet: This Data Sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
(c) 2005-2008 TERIDIAN Semiconductor Corporation
01/17/2008- Rev 4.3
Page: 46 of 46
(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3

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